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2.4GHz 802.11b Zero-IF Transceivers
AC ELECTRICAL CHARACTERISTICS — SYSTEM TIMING
(MAX2820/MAX2821 EV kit: V CC = +2.7V to +3.6V, f RF and f LO = 2400MHz to 2499MHz, f OSC = 22MHz or 44MHz, SHDNB = V IH ,
CSB = V IH , RBIAS = 12k ? , I CP = +2mA, BW LOOP = 45kHz, registers set to default power-up settings, T A = +25 ° C, unless otherwise
noted. Typical values are at V CC = +2.7V, f LO = 2437MHz, f OSC = 22MHz, unless otherwise noted.) (Note 11)
PARAMETER
Channel-Switching Time
RX/TX Turnaround Time
(Note 11)
Standby-to-Transmit Mode
Standby-to-Receive Mode
CONDITIONS
f LO = 2400MHz ? 2499MHz,
f LO settles to ± 10kHz (Note 9)
RX to TX, output settles to within ±2dB of final value of
output power, relative to rising edge of TX_ON
TX to RX, output settles to within ±2dB of final value of
output power, relative to rising edge of RX_ON
Standby to TX, output settles to within ±2dB of final value
of output power, relative to rising edge of TX_ON (Note 11)
Standby to RX, output settles to within ±2dB of final value
of output power, relative to rising edge of RX_ON (Note 11)
MIN
TYP
150
MAX
200
3
5
3
5
UNITS
μs
μs
μs
μs
AC ELECTRICAL CHARACTERISTICS — SERIAL INTERFACE TIMING
(MAX2820/MAX2821 EV kit: V CC = +2.7V to +3.6V, registers set to default power-up settings, T A = +25 ° C, unless otherwise noted.) (Note 11)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SERIAL INTERFACE TIMING (See Figure 1)
t CSO
t CSS
t DS
t DH
t CH
t CL
t CSH
t CSW
t CS1
f CLK
SCLK rising edge to CSB falling edge wait time
Falling edge of CSB to rising edge of first SCLK time
Data-to-serial clock setup time
Data-to-clock hold time
Serial clock pulse-width high
Clock pulse-width low
Last SCLK rising edge to rising edge of CSB
CSB high pulse width
Time between the rising edge of CSB and the next rising edge of SCLK
Clock frequency
5
5
5
10
10
10
5
10
5
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Parameters are production tested at +25 ° C only. Min/max limits over temperature are guaranteed by design and characterization.
Defined as the baseband differential RMS output voltage divided by the RMS input voltage (at the RF balun input).
Noise-figure specification excludes the loss of the external balun. The external balun loss is typically ~0.5dB.
CCK interferer at 25MHz offset. Desired signal equals -73dBm. Interferer amplitude increases until baseband output from
interferer is 10dB below desired signal. Adjacent channel rejection = P interferer - P desired .
Measured at balun input. Two CW tones at -43dBm with 15MHz and 25MHz spacing from the MAX2820/MAX2821 channel
frequency. IP3 is computed from 5MHz IMD3 product measured at the RX I/Q output.
Two CW interferers at -38dBm with 24.5MHz and 25.5MHz spacing from the MAX2820/MAX2821 channel frequency. IP2 is
computed from the 1MHz IMD2 product measured at the RX I/Q output.
Output power measured after the matching and balun. TX gain is set to maximum.
Adjacent and alternate channel power relative to the desired signal. TX gain is adjusted until the output power is -1dBm.
Power measured with 100kHz video BW and 100kHz resolution BW.
Time required to reprogram the PLL, change the operating channel, and wait for the operating channel center frequency to
settle within ± 10kHz of the nominal (final) channel frequency.
Note 10: Relative amplitude of reference spurious products appearing in the TX RF output spectrum relative to a CW tone at
0.5MHz offset from the LO.
Note 11: Min/max limits are guaranteed by design and characterization.
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